The electronic integrated memory device to which the embodiments of the invention are directed has eleven address outer pins, eight data pins and some control pins, among which are provided a synchronism or clock signal, CLK, and a signal used for setting the two IC interfaces provided.
Currently, testing flux software both for EWS or on-wafer testing and Final Test for testing on an assembled device has been intended for operation in the parallel mode.
Briefly, all the addresses and data under consideration have been used in the parallel mode during testing operation, whereas only the clock signal CLK and another four pins are necessary for the serial communication protocol.
As it is well known in the art, reading a memory location from the cell matrix requires that the address of the location is input first. This operation is usually performed according to a timing procedure, shown in FIG. 1 herewith attached.
Referring to the timing diagram of FIG. 1, the memory location addresses are input as two groups or packets of eleven bits each. The control RC falling and rising edges generate two latching pulses COL and ROW for the column and row of the matrix, respectively.
Thus, it is only at the end of a signal cycle RC that a complete address of the memory location to be read can be fully reconstructed. In other words, all of the internal reading timings start only at the end of the cycle RC.
More particularly, the rising edge of the control signal RC will cause the known ATD (Address Transition Detection) pulse, which will set off the whole reading mechanism.
FIG. 2 shows, by way of example, some of the signals that are present in the memory device during the reading operation; the arrows indicate the dependency of certain signals on other previously generated signals.
As mentioned, the rising edge of the signal RC sets off the ATD signal, which in turn will generate the signal READING and consequently the signal SALATCH, which stores data output from the reading sense amplifiers.
It can be appreciated that the address inputting mechanism described above is fairly complicated and it involves, especially while testing, a more elaborate control software and also extended duration for the whole testing procedure, which immediately results in increased cost of the integrated-memory-circuit product.
Therefore, a need has arisen for a novel testing procedure with appropriate functional features that allow the procedure to be carried out through the parallel interface, so that higher output levels than in the prior art can be achieved.